/*
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* Copyright (c) 2007 by NEC LE-IT: All rights reserved.
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* A transcription of ARMv6 atomic operations for the ARM Realview Toolchain.
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* This code works with armcc from RVDS 3.1
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* This is based on work in gcc/arm.h by
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* Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
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* Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
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* Copyright (c) 1999-2003 by Hewlett-Packard Company. All rights reserved.
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*
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*
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*
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* THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
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* OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
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*
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* Permission is hereby granted to use or copy this program
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* for any purpose, provided the above notices are retained on all copies.
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* Permission to modify the code and to distribute modified code is granted,
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* provided the above notices are retained, and a notice that the code was
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* modified is included with the above copyright notice.
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*
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*/
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#include "../test_and_set_t_is_ao_t.h" /* Probably suboptimal */
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#if __TARGET_ARCH_ARM < 6
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Dont use with ARM instruction sets lower than v6
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#else
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#define AO_ACCESS_CHECK_ALIGNED
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#define AO_ACCESS_short_CHECK_ALIGNED
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#define AO_ACCESS_int_CHECK_ALIGNED
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#include "../all_atomic_only_load.h"
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#include "../standard_ao_double_t.h"
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/* NEC LE-IT: ARMv6 is the first architecture providing support for simple LL/SC
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* A data memory barrier must be raised via CP15 command (see documentation).
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*
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* ARMv7 is compatible to ARMv6 but has a simpler command for issuing a
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* memory barrier (DMB). Raising it via CP15 should still work as told me by the
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* support engineers. If it turns out to be much quicker than we should implement
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* custom code for ARMv7 using the asm { dmb } command.
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*
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* If only a single processor is used, we can define AO_UNIPROCESSOR
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* and do not need to access CP15 for ensuring a DMB at all.
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*/
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AO_INLINE void
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AO_nop_full(void)
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{
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# ifndef AO_UNIPROCESSOR
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unsigned int dest=0;
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/* issue an data memory barrier (keeps ordering of memory transactions */
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/* before and after this operation) */
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__asm {
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mcr p15,0,dest,c7,c10,5
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};
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# else
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AO_compiler_barrier();
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# endif
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}
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#define AO_HAVE_nop_full
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/* NEC LE-IT: atomic "store" - according to ARM documentation this is
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* the only safe way to set variables also used in LL/SC environment.
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* A direct write won't be recognized by the LL/SC construct in other CPUs.
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*
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* HB: Based on subsequent discussion, I think it would be OK to use an
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* ordinary store here if we knew that interrupt handlers always cleared
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* the reservation. They should, but there is some doubt that this is
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* currently always the case for e.g. Linux.
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*/
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AO_INLINE void AO_store(volatile AO_t *addr, AO_t value)
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{
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unsigned long tmp;
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retry:
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__asm {
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ldrex tmp, [addr]
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strex tmp, value, [addr]
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teq tmp, #0
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bne retry
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};
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}
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#define AO_HAVE_store
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/* NEC LE-IT: replace the SWAP as recommended by ARM:
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"Applies to: ARM11 Cores
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Though the SWP instruction will still work with ARM V6 cores, it is recommended
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to use the new V6 synchronization instructions. The SWP instruction produces
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locked read and write accesses which are atomic, i.e. another operation cannot
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be done between these locked accesses which ties up external bus (AHB,AXI)
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bandwidth and can increase worst case interrupt latencies. LDREX,STREX are
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more flexible, other instructions can be done between the LDREX and STREX accesses.
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"
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*/
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#ifndef AO_PREFER_GENERALIZED
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AO_INLINE AO_TS_VAL_t
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AO_test_and_set(volatile AO_TS_t *addr) {
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AO_TS_VAL_t oldval;
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unsigned long tmp;
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unsigned long one = 1;
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retry:
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__asm {
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ldrex oldval, [addr]
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strex tmp, one, [addr]
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teq tmp, #0
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bne retry
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}
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return oldval;
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}
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#define AO_HAVE_test_and_set
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AO_INLINE AO_t
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AO_fetch_and_add(volatile AO_t *p, AO_t incr)
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{
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unsigned long tmp,tmp2;
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AO_t result;
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retry:
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__asm {
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ldrex result, [p]
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add tmp, incr, result
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strex tmp2, tmp, [p]
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teq tmp2, #0
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bne retry
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}
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return result;
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}
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#define AO_HAVE_fetch_and_add
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AO_INLINE AO_t
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AO_fetch_and_add1(volatile AO_t *p)
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{
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unsigned long tmp,tmp2;
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AO_t result;
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retry:
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__asm {
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ldrex result, [p]
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add tmp, result, #1
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strex tmp2, tmp, [p]
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teq tmp2, #0
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bne retry
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}
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return result;
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}
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#define AO_HAVE_fetch_and_add1
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AO_INLINE AO_t
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AO_fetch_and_sub1(volatile AO_t *p)
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{
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unsigned long tmp,tmp2;
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AO_t result;
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retry:
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__asm {
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ldrex result, [p]
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sub tmp, result, #1
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strex tmp2, tmp, [p]
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teq tmp2, #0
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bne retry
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}
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return result;
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}
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#define AO_HAVE_fetch_and_sub1
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#endif /* !AO_PREFER_GENERALIZED */
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#ifndef AO_GENERALIZE_ASM_BOOL_CAS
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/* Returns nonzero if the comparison succeeded. */
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AO_INLINE int
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AO_compare_and_swap(volatile AO_t *addr, AO_t old_val, AO_t new_val)
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{
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AO_t result, tmp;
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retry:
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__asm__ {
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mov result, #2
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ldrex tmp, [addr]
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teq tmp, old_val
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# ifdef __thumb__
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it eq
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# endif
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strexeq result, new_val, [addr]
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teq result, #1
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beq retry
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}
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return !(result&2);
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}
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# define AO_HAVE_compare_and_swap
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#endif /* !AO_GENERALIZE_ASM_BOOL_CAS */
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AO_INLINE AO_t
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AO_fetch_compare_and_swap(volatile AO_t *addr, AO_t old_val, AO_t new_val)
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{
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AO_t fetched_val, tmp;
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retry:
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__asm__ {
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mov tmp, #2
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ldrex fetched_val, [addr]
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teq fetched_val, old_val
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# ifdef __thumb__
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it eq
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# endif
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strexeq tmp, new_val, [addr]
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teq tmp, #1
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beq retry
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}
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return fetched_val;
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}
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#define AO_HAVE_fetch_compare_and_swap
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/* helper functions for the Realview compiler: LDREXD is not usable
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* with inline assembler, so use the "embedded" assembler as
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* suggested by ARM Dev. support (June 2008). */
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__asm inline double_ptr_storage AO_load_ex(const volatile AO_double_t *addr) {
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LDREXD r0,r1,[r0]
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}
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__asm inline int AO_store_ex(AO_t val1, AO_t val2, volatile AO_double_t *addr) {
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STREXD r3,r0,r1,[r2]
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MOV r0,r3
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}
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AO_INLINE AO_double_t
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AO_double_load(const volatile AO_double_t *addr)
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{
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AO_double_t result;
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result.AO_whole = AO_load_ex(addr);
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return result;
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}
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#define AO_HAVE_double_load
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AO_INLINE int
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AO_compare_double_and_swap_double(volatile AO_double_t *addr,
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AO_t old_val1, AO_t old_val2,
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AO_t new_val1, AO_t new_val2)
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{
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double_ptr_storage old_val =
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((double_ptr_storage)old_val2 << 32) | old_val1;
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double_ptr_storage tmp;
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int result;
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while(1) {
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tmp = AO_load_ex(addr);
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if(tmp != old_val) return 0;
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result = AO_store_ex(new_val1, new_val2, addr);
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if(!result) return 1;
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}
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}
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#define AO_HAVE_compare_double_and_swap_double
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#endif /* __TARGET_ARCH_ARM >= 6 */
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#define AO_T_IS_INT
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