/* FIXME. This is only a placeholder for the AIX compiler. */
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/* It doesn't work. Please send a patch. */
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/* Memory model documented at http://www-106.ibm.com/developerworks/ */
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/* eserver/articles/archguide.html and (clearer) */
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/* http://www-106.ibm.com/developerworks/eserver/articles/powerpc.html. */
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/* There appears to be no implicit ordering between any kind of */
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/* independent memory references. */
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/* Architecture enforces some ordering based on control dependence. */
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/* I don't know if that could help. */
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/* Data-dependent loads are always ordered. */
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/* Based on the above references, eieio is intended for use on */
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/* uncached memory, which we don't support. It does not order loads */
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/* from cached memory. */
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/* Thanks to Maged Michael, Doug Lea, and Roger Hoover for helping to */
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/* track some of this down and correcting my misunderstandings. -HB */
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#include "../all_aligned_atomic_load_store.h"
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void AO_sync(void);
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#pragma mc_func AO_sync { "7c0004ac" }
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#ifdef __NO_LWSYNC__
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# define AO_lwsync AO_sync
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#else
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void AO_lwsync(void);
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#pragma mc_func AO_lwsync { "7c2004ac" }
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#endif
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#define AO_nop_write() AO_lwsync()
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#define AO_HAVE_nop_write
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#define AO_nop_read() AO_lwsync()
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#define AO_HAVE_nop_read
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/* We explicitly specify load_acquire and store_release, since these */
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/* rely on the fact that lwsync is also a LoadStore barrier. */
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AO_INLINE AO_t
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AO_load_acquire(const volatile AO_t *addr)
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{
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AO_t result = *addr;
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AO_lwsync();
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return result;
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}
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#define AO_HAVE_load_acquire
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AO_INLINE void
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AO_store_release(volatile AO_t *addr, AO_t value)
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{
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AO_lwsync();
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*addr = value;
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}
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#define AO_HAVE_store_release
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#ifndef AO_PREFER_GENERALIZED
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/* This is similar to the code in the garbage collector. Deleting */
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/* this and having it synthesized from compare_and_swap would probably */
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/* only cost us a load immediate instruction. */
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/*AO_INLINE AO_TS_VAL_t
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AO_test_and_set(volatile AO_TS_t *addr) {
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# error FIXME Implement me
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}
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#define AO_HAVE_test_and_set*/
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AO_INLINE AO_TS_VAL_t
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AO_test_and_set_acquire(volatile AO_TS_t *addr) {
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AO_TS_VAL_t result = AO_test_and_set(addr);
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AO_lwsync();
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return result;
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}
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#define AO_HAVE_test_and_set_acquire
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AO_INLINE AO_TS_VAL_t
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AO_test_and_set_release(volatile AO_TS_t *addr) {
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AO_lwsync();
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return AO_test_and_set(addr);
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}
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#define AO_HAVE_test_and_set_release
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AO_INLINE AO_TS_VAL_t
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AO_test_and_set_full(volatile AO_TS_t *addr) {
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AO_TS_VAL_t result;
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AO_lwsync();
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result = AO_test_and_set(addr);
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AO_lwsync();
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return result;
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}
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#define AO_HAVE_test_and_set_full
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#endif /* !AO_PREFER_GENERALIZED */
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/*AO_INLINE AO_t
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AO_fetch_compare_and_swap(volatile AO_t *addr, AO_t old_val, AO_t new_val)
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{
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# error FIXME Implement me
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}
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#define AO_HAVE_fetch_compare_and_swap*/
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AO_INLINE AO_t
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AO_fetch_compare_and_swap_acquire(volatile AO_t *addr, AO_t old_val,
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AO_t new_val)
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{
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AO_t result = AO_fetch_compare_and_swap(addr, old_val, new_val);
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AO_lwsync();
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return result;
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}
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#define AO_HAVE_fetch_compare_and_swap_acquire
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AO_INLINE AO_t
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AO_fetch_compare_and_swap_release(volatile AO_t *addr, AO_t old_val,
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AO_t new_val)
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{
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AO_lwsync();
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return AO_fetch_compare_and_swap(addr, old_val, new_val);
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}
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#define AO_HAVE_fetch_compare_and_swap_release
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AO_INLINE AO_t
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AO_fetch_compare_and_swap_full(volatile AO_t *addr, AO_t old_val,
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AO_t new_val)
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{
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AO_t result;
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AO_lwsync();
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result = AO_fetch_compare_and_swap(addr, old_val, new_val);
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AO_lwsync();
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return result;
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}
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#define AO_HAVE_fetch_compare_and_swap_full
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/* TODO: Implement AO_fetch_and_add, AO_and/or/xor directly. */
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