/**
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* \file
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* Mapping of the arch memory model.
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*
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* Author:
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* Rodrigo Kumpera (kumpera@gmail.com)
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*
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* (C) 2011 Xamarin, Inc
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*/
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#ifndef _MONO_UTILS_MONO_MEMMODEL_H_
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#define _MONO_UTILS_MONO_MEMMODEL_H_
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#include <config.h>
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#include <mono/utils/mono-membar.h>
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/*
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In order to allow for fast concurrent code, we must use fencing to properly order
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memory access - specially on arch with weaker memory models such as ARM or PPC.
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On the other hand, we can't use arm's weak model on targets such as x86 that have
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a stronger model that requires much much less fencing.
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The idea of exposing each arch memory model is to avoid fencing whenever possible
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but at the same time make all required ordering explicit.
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There are four kinds of barriers, LoadLoad, LoadStore, StoreLoad and StoreStore.
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Each arch must define which ones needs fencing.
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We assume 3 kinds of barriers are available: load, store and memory (load+store).
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TODO: Add support for weaker forms of CAS such as present on ARM.
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TODO: replace all explicit uses of memory barriers with macros from this section. This will make a nicer read of lazy init code.
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TODO: if we find places where a data depencency could replace barriers, add macros here to help with it
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TODO: some arch with strong consistency, such as x86, support weaker access. We might need to expose more kinds of barriers once we exploit this.
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*/
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/*
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* Keep in sync with the enum in mini/mini-llvm-cpp.h.
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*/
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enum {
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MONO_MEMORY_BARRIER_NONE = 0,
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MONO_MEMORY_BARRIER_ACQ = 1,
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MONO_MEMORY_BARRIER_REL = 2,
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MONO_MEMORY_BARRIER_SEQ = 3,
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};
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#define MEMORY_BARRIER mono_memory_barrier ()
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#define LOAD_BARRIER mono_memory_read_barrier ()
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#define STORE_BARRIER mono_memory_write_barrier ()
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#if defined(__i386__) || defined(__x86_64__)
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/*
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Both x86 and amd64 follow the SPO memory model:
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-Loads are not reordered with other loads
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-Stores are not reordered with others stores
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-Stores are not reordered with earlier loads
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*/
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/*Neither sfence or mfence provide the required semantics here*/
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#define STORE_LOAD_FENCE MEMORY_BARRIER
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#define LOAD_RELEASE_FENCE MEMORY_BARRIER
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#define STORE_ACQUIRE_FENCE MEMORY_BARRIER
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#elif defined(__arm__)
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/*
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ARM memory model is as weak as it can get. the only guarantee are data dependent
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accesses.
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LoadStore fences are much better handled using a data depencency such as:
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load x; if (x = x) store y;
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This trick can be applied to other fences such as LoadLoad, but require some assembly:
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LDR R0, [R1]
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AND R0, R0, #0
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LDR R3, [R4, R0]
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*/
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#define STORE_STORE_FENCE STORE_BARRIER
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#define LOAD_LOAD_FENCE LOAD_BARRIER
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#define STORE_LOAD_FENCE MEMORY_BARRIER
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#define STORE_ACQUIRE_FENCE MEMORY_BARRIER
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#define STORE_RELEASE_FENCE MEMORY_BARRIER
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#define LOAD_ACQUIRE_FENCE MEMORY_BARRIER
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#define LOAD_RELEASE_FENCE MEMORY_BARRIER
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#elif defined(__s390x__)
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#define STORE_STORE_FENCE do {} while (0)
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#define LOAD_LOAD_FENCE do {} while (0)
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#define STORE_LOAD_FENCE do {} while (0)
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#define LOAD_STORE_FENCE do {} while (0)
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#define STORE_RELEASE_FENCE do {} while (0)
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#else
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/*default implementation with the weakest possible memory model */
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#define STORE_STORE_FENCE STORE_BARRIER
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#define LOAD_LOAD_FENCE LOAD_BARRIER
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#define STORE_LOAD_FENCE MEMORY_BARRIER
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#define LOAD_STORE_FENCE MEMORY_BARRIER
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#define STORE_ACQUIRE_FENCE MEMORY_BARRIER
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#define STORE_RELEASE_FENCE MEMORY_BARRIER
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#define LOAD_ACQUIRE_FENCE MEMORY_BARRIER
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#define LOAD_RELEASE_FENCE MEMORY_BARRIER
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#endif
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#ifndef STORE_STORE_FENCE
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#define STORE_STORE_FENCE
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#endif
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#ifndef LOAD_LOAD_FENCE
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#define LOAD_LOAD_FENCE
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#endif
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#ifndef STORE_LOAD_FENCE
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#define STORE_LOAD_FENCE
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#endif
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#ifndef LOAD_STORE_FENCE
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#define LOAD_STORE_FENCE
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#endif
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#ifndef STORE_RELEASE_FENCE
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#define STORE_RELEASE_FENCE
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#endif
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#ifndef LOAD_RELEASE_FENCE
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#define LOAD_RELEASE_FENCE
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#endif
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#ifndef STORE_ACQUIRE_FENCE
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#define STORE_ACQUIRE_FENCE
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#endif
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#ifndef LOAD_ACQUIRE_FENCE
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#define LOAD_ACQUIRE_FENCE
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#endif
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/*Makes sure all previous stores as visible before */
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#define mono_atomic_store_seq(target,value) do { \
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STORE_STORE_FENCE; \
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*(target) = (value); \
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} while (0)
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/*
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Acquire/release semantics macros.
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*/
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#define mono_atomic_store_release(target,value) do { \
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STORE_RELEASE_FENCE; \
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*(target) = (value); \
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} while (0)
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#define mono_atomic_load_release(_type,target) ({ \
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_type __tmp; \
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LOAD_RELEASE_FENCE; \
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__tmp = *(target); \
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__tmp; })
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#define mono_atomic_load_acquire(var,_type,target) do { \
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_type __tmp = *(target); \
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LOAD_ACQUIRE_FENCE; \
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(var) = __tmp; \
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} while (0)
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#define mono_atomic_store_acquire(target,value) { \
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*(target) = (value); \
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STORE_ACQUIRE_FENCE; \
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}
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#endif /* _MONO_UTILS_MONO_MEMMODEL_H_ */
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