/*
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* Copyright (c) 2005,2007 Thiemo Seufer <ths@networkno.de>
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*
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* THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
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* OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
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*
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* Permission is hereby granted to use or copy this program
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* for any purpose, provided the above notices are retained on all copies.
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* Permission to modify the code and to distribute modified code is granted,
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* provided the above notices are retained, and a notice that the code was
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* modified is included with the above copyright notice.
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*/
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/*
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* FIXME: This should probably make finer distinctions. SGI MIPS is
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* much more strongly ordered, and in fact closer to sequentially
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* consistent. This is really aimed at modern embedded implementations.
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* It looks to me like this assumes a 32-bit ABI. -HB
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*/
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#include "../all_aligned_atomic_load_store.h"
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#include "../loadstore/acquire_release_volatile.h"
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#include "../test_and_set_t_is_ao_t.h"
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/* Data dependence does not imply read ordering. */
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#define AO_NO_DD_ORDERING
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#ifdef AO_ICE9A1_LLSC_WAR
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/* ICE9 rev A1 chip (used in very few systems) is reported to */
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/* have a low-frequency bug that causes LL to fail. */
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/* To workaround, just issue the second 'LL'. */
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# define AO_MIPS_LL_FIX(args_str) \
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" ll " args_str "\n"
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#else
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# define AO_MIPS_LL_FIX(args_str) ""
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#endif
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AO_INLINE void
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AO_nop_full(void)
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{
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__asm__ __volatile__(
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" .set push \n"
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" .set mips2 \n"
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" .set noreorder \n"
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" .set nomacro \n"
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" sync \n"
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" .set pop "
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: : : "memory");
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}
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#define AO_HAVE_nop_full
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#ifndef AO_PREFER_GENERALIZED
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AO_INLINE AO_t
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AO_fetch_and_add(volatile AO_t *addr, AO_t incr)
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{
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register int result;
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register int temp;
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__asm__ __volatile__(
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" .set push\n"
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" .set mips2\n"
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" .set noreorder\n"
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" .set nomacro\n"
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"1: ll %0, %2\n"
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AO_MIPS_LL_FIX("%0, %2")
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" addu %1, %0, %3\n"
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" sc %1, %2\n"
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" beqz %1, 1b\n"
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" nop\n"
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" .set pop "
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: "=&r" (result), "=&r" (temp), "+m" (*addr)
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: "Ir" (incr)
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: "memory");
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return (AO_t)result;
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}
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#define AO_HAVE_fetch_and_add
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AO_INLINE AO_TS_VAL_t
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AO_test_and_set(volatile AO_TS_t *addr)
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{
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register int oldval;
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register int temp;
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__asm__ __volatile__(
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" .set push\n"
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" .set mips2\n"
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" .set noreorder\n"
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" .set nomacro\n"
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"1: ll %0, %2\n"
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AO_MIPS_LL_FIX("%0, %2")
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" move %1, %3\n"
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" sc %1, %2\n"
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" beqz %1, 1b\n"
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" nop\n"
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" .set pop "
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: "=&r" (oldval), "=&r" (temp), "+m" (*addr)
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: "r" (1)
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: "memory");
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return (AO_TS_VAL_t)oldval;
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}
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#define AO_HAVE_test_and_set
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/* TODO: Implement AO_and/or/xor primitives directly. */
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#endif /* !AO_PREFER_GENERALIZED */
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#ifndef AO_GENERALIZE_ASM_BOOL_CAS
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AO_INLINE int
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AO_compare_and_swap(volatile AO_t *addr, AO_t old, AO_t new_val)
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{
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register int was_equal = 0;
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register int temp;
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__asm__ __volatile__(
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" .set push \n"
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" .set mips2 \n"
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" .set noreorder \n"
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" .set nomacro \n"
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"1: ll %0, %1 \n"
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AO_MIPS_LL_FIX("%0, %1")
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" bne %0, %4, 2f \n"
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" move %0, %3 \n"
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" sc %0, %1 \n"
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" .set pop \n"
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" beqz %0, 1b \n"
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" li %2, 1 \n"
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"2: "
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: "=&r" (temp), "+m" (*addr), "+r" (was_equal)
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: "r" (new_val), "r" (old)
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: "memory");
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return was_equal;
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}
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# define AO_HAVE_compare_and_swap
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#endif /* !AO_GENERALIZE_ASM_BOOL_CAS */
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AO_INLINE AO_t
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AO_fetch_compare_and_swap(volatile AO_t *addr, AO_t old, AO_t new_val)
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{
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register int fetched_val;
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register int temp;
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__asm__ __volatile__(
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" .set push\n"
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" .set mips2\n"
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" .set noreorder\n"
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" .set nomacro\n"
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"1: ll %0, %2\n"
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AO_MIPS_LL_FIX("%0, %2")
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" bne %0, %4, 2f\n"
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" move %1, %3\n"
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" sc %1, %2\n"
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" beqz %1, 1b\n"
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" nop\n"
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" .set pop\n"
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"2:"
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: "=&r" (fetched_val), "=&r" (temp), "+m" (*addr)
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: "r" (new_val), "Jr" (old)
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: "memory");
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return (AO_t)fetched_val;
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}
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#define AO_HAVE_fetch_compare_and_swap
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/* #include "../standard_ao_double_t.h" */
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/* TODO: Implement double-wide operations if available. */
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/* CAS primitives with acquire, release and full semantics are */
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/* generated automatically (and AO_int_... primitives are */
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/* defined properly after the first generalization pass). */
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/* FIXME: 32-bit ABI is assumed. */
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#define AO_T_IS_INT
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